發明人

王朝欽教授

系所

電機系

專利名稱

具製程、電壓及溫度補償之二倍供應電壓共容輸入輸出緩衝器/2xVDD-TOLERANT LOGIC CIRCUITS AND A RELATED

證書號

US 7,932,748 B1

公告日期

100年4月26日

專利摘要

A 2.times.VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2.times.VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2.times.VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2.times.VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

技轉服務窗口

洪勝鴻先生(分機2625)